“With its first 90nm read channel product Infineon is well on track to deliver the next generation of ICs for the growing HDD market,” stated Peter Bauer, member of the management board and head of Infineon’s Automotive, Industrial and Multimarket business group. “Our commitment to the market and long presence is based on a broad IP portfolio which covers allmost all interfaces, low power and state-of-the-art SOC design methodology, as well as technologies now becoming very important to the HDD industry such as Non-volatile memories and Security Chip Card solutions.”

“Migration to 90nm of the Infineon read channel core enables the HDD industry to meet next generation product requirements, including higher data rates, reduced power consumption and smaller die-size leading to advanced SOC solutions at competitive cost. The first tested read channel core silicon has demonstrated that the PLL is able to reach up to 3.6GHz speed and that the Analog Front-End signal path allows for datarates up to 2.7Gb/s. This is an increase of approx. 50% compared to advanced Read Channels in 130nm technologies,” said Sandro Cerato, General Manager and Vice President at Infineon ADS - ASIC and Design Solutions.

The Hard Disk Drive market is expected to grow by almost 30 percent from US Dollar 3.3bn in 2005 to US Dollar 4.5bn in 2009 according to a research by Gartner Dataquest in August 2005 mainly driven by mobile and desktop applications.

“The development of this read channel technology further demonstrates Hitachi’s and Infineon’s innovative strengths and engineering expertise,” said Steven Smith, Senior Director & General Manager of Rochester MN, Hitachi GST. “Infineon has demonstrated leadership in silicon development and integration and we are very pleased with the performance of our first 90nm read channel implementation.”

The new read channel technology generation supports advanced features such as perpendicular recording and leverages on 2^nd generation Reverse Concatenation coding to deliver state-of-the-art signal-to-noise-ratio (SNR) performance for significantly improved storage densities.

Infineon’s 90nm read channel technology leverages on a common architecture and is applicable to all HDD segments (Enterprise, Desktop, Mobile and Ultra-Low-Power). The requirements of the different HDD platforms are achieved by customizing the designs to the specific target parameters of each market segment.

A second implementation, currently in development for battery operated applications, targets an exceptionally low power dissipation. It will also provide superior stand-by power and leakage current performance thanks to Infineon’s 90nm process technology that is designed to support handheld applications such as cellular phones.

The new read-write channel has been implemented in Infineon's 90nm CMOS technology which provides the capabilities of combining high performance, low power and analog devices in the same silicon for various applications. Infineon's technology and design system allows for product specific and cost effective optimizations for mixed signal and advanced digital signal processing in a single chip ranging from performance intensive enterprise-class server applications to power sensitive mobile consumer electronic applications. Key features of the technology are the ability to integrate multiple threshold voltages and multiple gate oxide devices with minimum physical gate dimensions down to 70nm using advanced power saving concepts like active wells, clock-gating and micro-switches with 6 to 9 layers of Copper metallization in a single chip.

The new HDD controller from the Infineon ASIC and Design Solutions Group can be manufactured worldwide in multiple fabs, providing customers with supply-chain flexibility and opportunity to expand which is a very important value proposition in the hard drive industry. Fabs currently offering Infineon's 90nm technology include Infineon's Dresden fab in Germany and UMC in Taiwan.