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New Features
- Added 'SPDREPORTBYELO' and 'SPDREPORTBYTEHI' configuration parameter for specifying the SPD byte range to display in the HTML report
- Implemented workaround for reading DDR5 SPD when SPD write disable (SPDWR) is set for Intel chipsets
- Added DIMM/IC decoding support for AMD Phoenix (19h 74h) chipsets
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Fixes/Enhancements
- Added support for chipsets with up to 12 memory controllers
- Fixed hang due to reading non-existent MSR registers for AMD 19h 60-6fh chipsets
- Fixed channel decoding for AMD Ryzen Zen 2/4 chipsets
- Fixed incorrect memory clock reported for Intel Alder Lake/Rocket Lake chipsets
- Fixed incorrect memory clock reported for AMD 19h 60-6fh chipsets
- Fixed incorrect CPU temperature reported for EPYC 7003 series chipsets due to temperature offsets
- Fixed DIMM temperature read failure after reading SPD for certain DDR5 modules
- Added reporting of additional DDR5 SPD attributes
- Fixed hang due memory allocation issues for Intel Skylake/Kaby Lake chipsets
- Added ECC support for additional Intel Skylake-SP chipset variants
- Added workaround for hang when obtaining list of benchmark results
- Perform cache invalidation before start of the RAM benchmark test to fix result inconsistencies
- Fixed text being unaligned when containing full-width characters
- Updated localization strings
- Updated blacklist
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